In IC designs, computer simulation processes are used to check integrity of the design and predict behavior of a resulting circuit. However, traditional computer simulation processes fail to capture a significant degradation in performance due to a physical placement of devices in the IC design, particularly with respect to stacked devices. As such, IC designs verified using traditional computer simulation processes may, nonetheless, contain unknown and significant degraded performance that impacts the manufacturing yield of a resulting IC circuit.
A need therefore exists for methodology enabling a verification of IC designs that compensates for degraded performance due to a physical placement, particularly a stacked physical placement.